logic - If statement and assiging wires in Verilog - Stack Overflow 2013年7月19日 - And you cant assign wires inside an always block, you have to use reg ... In this case 2 bits, since you want to ask for 00; input a; input b; output out; reg x; always ...
'assign' a value to an output reg in Verilog? - Stack Overflow 2009年11月27日 - In this case, you'll need code that looks something like this: // some parameter ...
